SNIA’s Compute+Memory+Storage Summit is where architectures, solutions, and community come together. Our 2023 Summit – taking place virtually on April 11-12, 2023– is the best example to date, featuring a stellar lineup of 50 speakers in 40 sessions covering topics including computational storage real-world applications, the future of memory, critical storage security issues, and the latest on SSD form factors, CXL™, and UCIe™.
“We’re excited to welcome executives, architects, developers, implementers, and users to our 11th annual Summit,” said David McIntyre, C+M+S Summit Co-Chair, and member of the SNIA Board of Directors. “We’ve gathered the technology leaders to bring us the latest developments in compute, memory, storage, and security in our free online event. We hope you will watch live to ask questions of our experts as they present, and check out those sessions you miss on-demand.”
Memory sessions begin with Watch Out – Memory’s Changing! where Jim Handy and Tom Coughlin will discuss the memory technologies vying for the designer’s attention, with CXL™ and UCIe™ poised to completely change the rules. Speakers will also cover thinking memory, optimizing memory using simulations, providing capacity and TCO to applications using software memory tiering, and fabric attached memory.
Compute sessions include Steven Yuan of StorageX discussing the Efficiency of Data Centric Computing, and presentations on the computational storage and compute market, big-disk computational storage arrays for data analytics, NVMe as a cloud interface, improving storage systems for simulation science with computational storage, and updates on SNIA and NVM Express work on computational storage standards.
CXL and UCIe will be featured with presentations on CXL 3.0 and Universal Compute Interface Express™ On-Package Innovation Slot for Compute, Memory, and Storage Applications.
The Summit will also dive into security with a introductory view of today’s storage security landscape and additional sessions on zero trust architecture, storage sanitization, encryption, and cyber recovery and resilience.
For 2023, the Summit is delighted to present three panels – one on Exploring the Compute Express Link™ (CXL™) Device Ecosystem and Usage Models moderated by Kurtis Bowman of the CXL Consortium, one on Persistent Memory Trends moderated by Dave Eggleston of Microchip, and one on Form Factor Updates, moderated by Cameron Brett of the SNIA SSD Special Interest Group.
We will also feature the popular SNIA Birds-of-a-Feather sessions. On Tuesday April 11 at 4:00 pm PDT/7:00 pm EDT, you can join to discuss the latest compute, memory, and storage developments, and on Wednesday April at 3:00 pm PDT/6:00 pm EDT, we’ll be talking about memory advances.
For 11 years, SNIA Compute, Memory and Storage Initiative (CMSI) has presented a Summit featuring industry leaders speaking on the key topics of the day. In the early years, it was persistent memory-focused, educating audiences on the benefits and uses of persistent memory. In 2020 it expanded to a Persistent Memory+Computational Storage Summit, examining that new technology, its architecture, and use cases.
Now in 2023, the Summit is expanding again to focus on compute, memory, and storage. In fact, we’re calling 2023 the Year of the Summit – a year to get back to meeting in person and offering a variety of ways to listen to leaders, learn about technology, and network to discuss innovations, challenges, solutions, and futures.
We’re delighted that our first event of the Year of the Summit is a networking event at MemCon, taking place March 28-29 at the Computer History Museum in Mountain View CA.
At MemCon, SNIA CMSI member and IEEE President elect Tom Coughlin of Coughlin Associates will moderate a panel discussion on Compute, Memory, and Storage Technology Trends for the Application Developer. Panel members Debendra Das Sharma of Intel and the CXL™ Consortium, David McIntyre of Samsung and the SNIA Board of Directors, Arthur Sainio of SMART Modular and the SNIA Persistent Memory Special Interest Group, and Arvind Jaganath of VMware and SNIA CMSI will examine how applications and solutions available today offer ways to address enterprise and cloud provider challenges – and they’ll provide a look to the future.
SNIA leaders will be on hand to discuss work in computational storage, smart data acceleration interface (SDXI), SSD form factor advances, and persistent memory trends. Share a libation or two at the SNIA hosted networking reception on Tuesday evening, March 28.
This inaugural MemCon event is perfect to start the conversation, as it focuses on the intersection between systems design, memory innovation (emerging memories, storage & CXL) and other enabling technologies. SNIA colleagues and friends can register for MemCon with a 15% discount using code SNIA15.
April 2023 Networking!
We will continue the Year with a newly expanded SNIA Compute+Memory+Storage Summit coming up April 11-12 as a virtual event. Complimentary registration is now open for a stellar lineup of speakers, including Stephen Bates of Huawei, Debendra Das Sharma of Universal Chiplet Interconnect Express™, Jim Handy of Objective Analysis, Shyam Iyer of Dell, Bill Martin of Samsung, Jake Oshins of Microsoft, Andy Rudoff of Intel, Andy Walls of IBM, and Steven Yuan of StorageX.
Summit topics include Memory’s Headed for Change, High Performance Data Analytics, CXL 3.0, Detecting Ransomware, Meeting Scaling Challenges, Open Standards for Innovation at the Package Level, and Standardizing Memory to Memory Data Movement. Great panel discussions are on tap as well. Kurt Lender of the CXL Consortium will lead a discussion on Exploring the CXL Device Ecosystem and Usage Models, Dave Eggleston of Microchip will lead a panel with Samsung and SMART Modular on Persistent Memory Trends, and Cameron Brett of KIOXIA will lead a SSD Form Factors Update. More details at www.snia.org/cms-summit.
Enterprise
and Data Center Form Factor (EDSFF) technologies have come a long way since our
2020 SNIA CMSI webinar on the topic.
While that webinar still provides an outstanding framework for
understanding – and SNIA’s popular SSD Form Factors page gives the latest on the E1 and E3 specifications – SNIA Solid State Drive Special Interest Group co-chairs Cameron Brett and
Jonmichael Hands joined to provide the latest updates at our live webcast: EDSFF
Taking Center Stage in the Data Center. We had some
great questions from our live audience, so our experts have taken the time to
answer them in this this blog.
Q: What does the EDSFF roadmap look like? When will we see PCIe® Gen5 NVMe™, 1.2, 2.0 CXL™cx devices?
As the form factors come out into the market, we anticipate that there will be feature updates and smaller additions to the existing specifications like SFF TA 1008 and SFF TA 1023. There may also be changes around defining LEDs and stack updates. The EDSFF specifications, however, are mature and we have seen validation and support on the connector and how it works at higher interface speeds. You now have platforms, backplanes, and chassis to support these form factors in the marketplace. Going forward, we may see integration with other device types like GPUs, support of new platforms, and alignment with PCIe Gen 5. Regarding CXL, we see the buzz, and having this form factor be the kind of vehicle for CXL will have a huge momentum.
Q: I’m looking for thoughts on recent comments I read about PCIe5 NVMe drives likely needing/benefitting from larger form-factors (like 25mm wide vs 22) for cooling considerations. With mass market price optimizations, what is the likelihood that client compute will need to transition away from existing M.2 (esp 2280) form factors in the coming years and will that be a shared form-factor shared with server compute (as has been the case with 5.25″,3.5″,2.5″ drives)?
We are big fans of EDSFF being placed on reference platforms for OEMs and motherboard makers. Enterprise storage support would be advantageous on the desktop. At the recent OCP Global Summit, there was discussion on Gen 5 specifications and M.2 and U.2. With the increased demands for power and bandwidth, we think if you want more performance you will need to move to a different form factor, and EDSFF makes sense.
Q: On E1.S vs E3.S market dominance, can you refer to their support on dual-port modules? Some traditional storage server designs favor E3.S because of the dual port configuration. More modern storage designs do not rely on dual port modules, and therefore prefer E1.S. Do you agree to this correlation ? How will this affect the predictions on market share?
A: There is some confusion about the
specification support versus what vendors support and what customers are
demanding. The EDSFF specifications
share a common pin out and connection specifications. If a manufacturer wishes to support the dual
port functionality, they can do so now.
Hyperscalers are now using E1.S in compute designs and may use E3 for
their high availability enterprise storage requirements. Our webcast showed the forecast from Forward
Insights on larger shipments of E3 further out in time, reflecting the
transition away from 2.5-inch to E3 as server and storage OEMs transition their
backplanes.
Q: Have you investigated enabling conduction cooling of E1.S and
E3.S to a water cooled cold plate? If not, is it of interest?
OCP Global Summit featured a presentation from
Intel about immersion cooling with a focus on the sustainability aspect as you
can get your power usage effectiveness (PUE) down further by eliminating the
fans in system design while increasing cooling.
There doesn’t seem to be anything eliminating the use of EDSFF drives
for immersion cooling. New CPUs have heat pipes, and new OEM designs have up to
36 drives in a 2U chassis. How do you
cool that? Many folks are talking about
cooling in the data center, and we’ll just need to wait to see what happens!
Illustration of Dell PowerEdge AMD Genoa Servers with 32 E3.S SSD bays
Thanks again for your interest in SNIA and Enterprise and Data Center SSD Form Factors. We invite you to visit our SSD Form Factor page where we have videos, white papers, and charts explaining the many different SSD sizes and formats in a variety of form factors. You may also wish to check out a recent article from Storage Review which discusses an E3.S implementation.
Version 1.0 of the SNIA Computational Storage Architecture and Programming Model has just been released to the public at www.snia.org/csarch. The Model has received industry accolades, winning the Flash Memory Summit 2022 Best of Show Award for Most Innovative Memory Technology at their recent conference. Congratulations to all the companies and individuals who contributed large amounts of expertise and time to the creation of this Model.
SNIAOnStorage sat down with SNIA Computational Storage Technical Work Group (CS TWG) co-chairs Jason Molgaard and Scott Shadley; SNIA Computational Storage Architecture and Programming Model editor Bill Martin; and SNIA Computational Storage Special Interest Group chair David McIntyre to get their perspectives on this milestone release and next steps for SNIA.
SNIAOnStorage (SOS): What is the significance of a 1.0
release for this computational storage SNIA specification?
Bill Martin (BM): The
1.0 designation indicates that the SNIA membership has voted to approve the
SNIA Computational Storage Architecture and Programming Model as an official
SNIA specification. This means that our
membership believes that the architecture is something that you can develop
computational storage-related products to where multiple vendor products will
have similar complimentary architectures and with an industry standardized
programming model.
Jason Molgaard (JM): The 1.0 release also indicates a level
of maturity where companies can implement computational storage that reflects
the elements of the Model. The SNIA CS
TWG took products into account when defining the Model’s reference architecture. The Model is for everyone – even those who
were not part of the 52 participating companies and 258 member representatives in
the TWG – this is concrete, and they can begin development today.
SNIA Computational Storage Technical Work Group Company Members
SOS: What do you think is the most important feature of the 1.0 release?
Scott Shadley (SS):
Because we have reached the 1.0 release, there is no one specific area
that makes one feature more important than anything else. The primary difference from the last release
and 1.0 was addressing the Security section. As we know, there are many new
security discussions happening and we want to ensure our architecture doesn’t
break or even create new security needs. Overall, all aspects are key and
relevant.
JM: I agree. The entire Model is applicable to product development and is a comprehensive and inclusive specification. I cannot point to a single section to that is subordinate to other sections in the Model.
David McIntyre (DM):
It’s an interesting time for these three domains – compute, storage, and
networking – which are beginning to merge and support each other. The 1.0 Model has a nice baseline on definitions
– before this there were none, but now we have Computational Storage Devices (CSxes),
(Computational Storage Processors (CSPs), Computational Storage Drives (CSDs),
and Computational Storage Arrays (CSAs)), and more; and companies can better
define what is a CSP and how it connects to associated storage. Definitions
help to educate and ground the ecosystems and the engineering community, and
how to characterize our vendor solutions into these categories.
BM: I would say that the
four most important parts of the 1.0 Model are:
1) it defines terminology that can be used across different protocols; 2)
it defines a discovery process flow for those architectures; 3) it defines
security considerations for those architectures; and 4) it gives users some
examples that can be used for those architectures.
SOS: Who do you
see as the audience/user for the Model?
What should these constituencies do with the Model?
JM: The Model is useful for both hardware developers who are
developing their own computational storage systems, as well as software architects,
programmers, and other users to be educated on definitions and the common
framework that the architecture describes for computational storage. This will
enable everyone to be on the same playing field. The intent is for everyone to have the same
level of understanding and to carry on conversations with internal and external
developers that are working on related projects. Now they can speak on the same
plane. Our wish is for folks to adhere
to the model and follow it in their product development.
DM: Having an industry developed reference architecture that
hardware and application developers refer to is an important attribute of the
1.0 specification, especially as we get into cloud to edge deployment where
standardization has not been as early.
Putting compute where data is at the edge – where data is being driven –
gives the opportunity to provide normalization and standardization that application
developers can refer to contributing computational storage solutions to the edge
ecosystem.
SS: Version 1.0 is designed with customers to be used as a full
reference document. It is an opportunity
to highlight that vendors and solutions providers are doing it in a directed
and unified way. Customers with a multi-sourcing
strategy see this as something that resonates well to drive involvement with
the technology.
SOS: Are there other activities within SNIA going along
with the release of the Model?
BM: The CS TWG is
actively developing a Computational Storage API that will utilize the Model and
provide an application programming interface for which vendors can provide a
library that maps to their particular protocol, which would include the NVMe®
protocol layer.
JM: The TWG is also collaborating with the SNIA Smart Data Accelerator Interface (SDXI) Technical Work Group on how SDXI and computational storage can potentially be combined in the future.
There is a good opportunity for security to continue to be a
focus of discussion in the TWG – examining the threat matrix as the Model
evolves to ensure that we are not recreating or disbanding what is out there –
and that we use existing solutions.
DM: From a security
standpoint the Model and the API go hand in hand as critical components far
beyond the device level. It is very
important to evolve where we are today from device to solution level
capabilities. Having this group of
specifications is very important to contribute to the overall ecosystem.
SOS: Are there any industry activities going along with the release of version 1.0 of the Model?
BM: NVM Express®
is continuing their development effort on computational storage programs and Subsystems
Local Memory that will provide a mechanism to implement the SNIA Architecture
and Programming Model.
JM: Compute Express Link™ (CXL™) is a logical progression for
computational storage from an interface perspective. As time moves forward, we look for much work
to be done in that area.
SS: We know from Flash Memory Summit 2022 that CXL is a next
generation transport planned for both storage and memory devices. CXL focuses on memory today and the high-speed
transport expected there. CXL is the basically the transport beyond NVMe. One
key feature of the SNIA Architecture and Programming Model is to ensure it can apply
to CXL, Ethernet, or other transports as it does not dictate the transport
layer that is used to talk to the Computational Storage Devices (CSxes).
DM: Standards bodies
have been siloed in the past. New opportunities of interfaces and protocols
that work together harmoniously will better enable alliances to form. Grouping of standards that work together will
better support application requirements from cloud to edge.
SOS: Any final
thoughts?
BM: You may ask “Will there be a next generation of the
Model?” Yes, we are currently working on the next generation with security
enhancements and any other comments we get from public utilization of the
Model. Comments can be sent to the SNIA
Feedback Portal.
DM: We also welcome input from other industry organizations
and their implementations.
BM: For example, if there are implications to the Model from
work done by CXL, they could give input and the TWG would work with CXL to
integrate necessary enhancements.
JM: CXL could develop new formats specific to Computational Storage. Any new commands could still align with the
model since the model is transport agnostic.
SOS: Thanks for your time in discussing the Model. Congratulations on the 1.0 release! And for our readers, check out these links for more information on computational storage:
In our recent webcast Is the Data Really Gone? A Primer on the Sanitization of Storage Devices, our presenters Jonmichael Hands (Chia Network), Jim Hatfield (Seagate), and John Geldman (KIOXIA) took an in-depth look at exactly what sanitization is, what the standards are, and where sanitization is being practiced today. If you missed it, you can watch on-demand their recommendations for the verification of sanitization to ensure that devices are meeting stringent requirements – and access the presentation slides at the SNIA Educational Library. Here, in our Q&A blog, our experts answer more of your questions on data sanitization.
Is Over Provisioning part of the spare
blocks or separate?
The main intent of an
overprovisioning strategy is to resolve the asymmetric NAND behaviors of Block
Erase (e.g., MBs) and Page Write (e.g., KBs) that allows efficient use of a
NAND die’s endurance capability, in other words, it is a store-over capability
that is regularly used leaving older versions of a Logical Block Addressing (LBA)
in media until it is appropriate to garbage collect.
Spares are a subset of overprovisioning and a spare block
strategy is different than an overprovisioning strategy. The main intent of a spare strategy is a
failover capability mainly used on some kind of failure (this can be a
temporary vibration issue on a hard disk drive or a bad sector).
The National
Institute of Standards and Technology (NIST) mentions the NVMe®
Format with Secure Erase Settings to 1 for User Data erase or 2 for Crypto as a
purge method. From what I can gather the sanitize was more a fallout of the
format rather than anything that was designed. With the NVMe sanitize would you
expect the Format with the Data Erasure options to be depreciated or moved back
to a clear?
The Format NVM command does
have a crypto erase, but it is entirely unspecified, vendor specific, and
without any requirements. It is not to be trusted. Sanitize, however, can be
trusted, has specific TESTABLE requirements, and is sanctioned by IEEE 2883.
The Format NVM command was
silent on some requirements that are explicit in both NVMe Sanitize commands
and IEEE 2883. It was possible, but not required for a NVME Format with Secure
Erase Settings set to Crypto to also purge other internal buffers. Such
behavior beyond the specification is vendor specific. Without assurance from
the vendor, be wary of assuming the vendor made additional design efforts. The
NVMe Sanitize command does meet the requirements of purge as defined in IEEE
2883.
My question is around logical
(file-level, OS/Filesystem, Logical volumes, not able to apply to physical
DDMs): What can be done at the technical level and to what degree that it is
beyond what modern arrays can do (e.g., too many logical layers) and thus, that
falls under procedural controls. Can you comment on regulatory alignment with
technical (or procedural) acceptable practices?
The IEEE Security in Storage
Working Group (SISWG) has not had participation by subject matter experts for
this, and therefore has not made any requirements or recommendations, and
acceptable practices. Should such experts participate, we can consider
requirements and recommendations and acceptable practices.
Full
verification is very expensive especially if you are doing lots of drives
simultaneously. Why can’t you seed like you could do for crypto, verify the
seeding is gone, and then do representative sampling?
The problem with seeding
before crypto erase is that you don’t know the before and after data to
actually compare with. Reading after crypto erase returns garbage…. but you
don’t know if it is the right garbage.
In addition, in some implementations, doing a crypto erase also destroys
the CRC/EDC/ECC information making the data unreadable after crypto erase.
Seeding is not a common
defined term. If what was intended by seeding was writing known values into known
locations, be aware that there are multiple problems with that process.
Consider an Overwrite Sanitize operation. Such an operation writes the same
pattern into every accessible and non-accessible block. That means that the
device is completely written with no free media (even the overprovisioning has
that pattern). For SSDs, a new write into that device has to erase data before
it can be re-written. This lack of overprovisioned data in SSDs results in
artificial accelerated endurance issues.
A common solution
implemented by multiple companies is to de-allocate after sanitization. After a
de-allocation, a logical block address will not access physical media until
that logical block address is written by the host. This means that even if
known data was written before sanitize, and if the sanitize did not do its job,
then the read-back will not return the data from the physical media that used
to be allocated to that address (i.e., that physical block is de-allocated) so
the intended test will not be effective.
Are there other
problems with Sanitize?
Another problem with
Sanitize is that internal protection information (e.g., CRC data, Integrity
Check data, and Error Correction Code data) have also been neutralized until
that block is written again with new data. Most SSDs are designed to never
return bad data (e.g., data that fails Integrity Checks) as a protection and
reliability feature.
What are some
solutions for Data Sanitization?
One solution that has been
designed into NVMe is for the vendor to support a full overwrite of media after
a crypto erase or a block erase sanitize operation. Note that such an overwrite
has unpopular side-effects as the overwrite:
changes any result of the actual sanitize
operation;
may take a significant time (e.g., multiple
days); and
still requires a full-deallocation by the
host to make the device useful again.
A unique complication for
a Block Erase sanitization operation that leaves NAND in an erased state is not
stable at the NAND layer, so a full write of deallocated media can be scheduled
to be done over time, or the device can be designed to complete an overwrite
before the sanitize operation returns a completion. In any/either case, the
media remains deallocated until the blocks are written by the host.
Can you kindly
clarify DEALLOCATE all storage before leaving sanitize ? What does that mean
physically?
Deallocation (by itself) is
not acceptable for sanitization. It is allowable AFTER a proper and thorough
sanitization has taken place. Also, in some implementations, reading a
deallocated logical block results in a read error. Deallocation must be USED
WITH CAUTION. There are many knobs and switches to set to do it right.
Deallocation means removing
the internal addressing that mapped a logical block to a physical block. After
deallocation, media is not accessed so the read of a logical block address
provides no help in determining if the media was actually sanitized or not.
Deallocation gives as factory-fresh out of the box performance as is possible.
SNIA is pleased to be part of the Flash Memory Summit 2022 agenda
August 1-4, 2022 at the Santa Clara CA Convention Center, with our volunteer leadership
demonstrating solutions, chairing and speaking in sessions, and networking with
FMS attendees at a variety of venues during the conference.
The ever-popular SNIA Reception at FMS features the SNIA groups Storage Management Initiative, Compute Memory and Storage Initiative, and Green Storage Initiative, along with SNIA alliance partners CXL Consortium, NVM Express, and OpenFabrics Alliance. Stop by B-203/204 at the Convention Center from 5:30 – 7:00 pm Monday August 1 for refreshments and networking with colleagues to kick off the week!
You won’t want to miss SNIA’s mainstage presentation on Wednesday August 3 at 2:40 pm in the Mission City Ballroom. SNIA Vice Chair Richelle Ahlvers of Intel will provide a perspective on how new storage technologies and trends are accelerating through standards and open communities.
In the Exhibit Hall, SNIA Storage Management Initiative and Compute Memory and Storage Initiative are FMS Platinum sponsors with a SNIA Demonstration Pavilion at booth #725. During exhibit hours Tuesday evening through Thursday afternoon, 15 SNIA member companies will be featured in live technology demonstrations on storage management, computational storage, persistent memory, sustainability, and form factors; a Persistent Memory Programming Workshop and Hackathon; and theater presentations on SNIA’s standards and alliance work.
Long standing SNIA technology focus areas in computational storage and memory will be represented in the SNIA sponsored System Architectures Track (SARC for short) – Tuesday for memory and Thursday for computational storage. SNIA is also pleased to sponsor a day on CXL architectures, memory, and storage talks on Wednesday. These sessions will all be in Ballroom G.
A new Sustainability Track on Thursday morning in Ballroom A led by the SNIA Green Storage Technical Work Group includes presentations on SSD power management, real world applications and storage workloads, and a carbon footprint comparison of SSDs vis HDDs, followed by a panel discussion. SSDs will also be featured in two SNIA-led presentation/panel pairs – SSDS-102-1 and 102-2 Ethernet SSDs on Tuesday afternoon in Ballroom B and SSDS-201-1 and 201-2 EDSFF E1 and E3 form factors on Wednesday morning in Ballroom D. SNIA Swordfish will be discussed in the DCTR-102-2 Enterprise Storage Part 2 session in Ballroom D on Tuesday morning
And the newest SNIA technical work group – DNA Data Storage– will lead a new-to-2022 FMS track on Thursday morning in Great America Meeting Room 2, discussing topics like preservation of DNA for information storage, the looming need for molecular storage, and DNA sequencing at scale. Attendees can engage for questions and discussion in Part 2 of the track.
Additional
ways to network with SNIA colleagues include the always popular chat with the
experts – beer and pizza on Tuesday evening, sessions on cloud storage, artificial
intelligence, blockchain, and an FMS theater presentation on real world storage
workloads.
Full details on session times, locations, chairs and speakers for all these exciting FMS activities can be found at www.snia.org/fms and on the Flash Memory Summit website. SNIA colleagues and friends can register for $100.00 off the full conference or single day packages using the code SNIA22 at www.flashmemorysummit.com.
Last month’s SNIA Persistent Memory and Computational
Storage Summit (PM+CS Summit) put on a great show with 35 technology
presentations from 41 speakers. Every presentation is now available online with
a video and PDF found at www.snia.org/pm-summit.
Recently, SNIA On Storage sat down with David McIntyre, Summit Chair from Samsung, on his impressions of this 10th annual event.
SNIA On Storage (SOS): What were your thoughts on key topics coming into the Summit and did they change based on the presentations?
David McIntyre (DM): We were excited to attract technology leaders to speak on the state of computational storage and persistent memory. Both mainstage and breakout speakers did a good job of encapsulating and summarizing what is happening today. Through the different talks, we learned more about infrastructure deployments supporting underlying applications and use cases. A new area where attendees gained insight was computational memory.
I find it encouraging that as an industry we are moving forward
on focusing on applications and use cases, and supporting software and
infrastructure that resides across persistent memory and computational storage. And with computational memory, we are now
getting more into the system infrastructure concerns and making these
technologies more accessible to application developers.
SOS: Any sessions you want to recommend to
viewers?
DM: We had great feedback on our speakers during the live
event. Several sessions I might
recommend are Gary
Grider of Los Alamos National Labs (LANL), who explained how computational
storage is being deployed across his lab; Chris Petersen of
Meta, who took an infrastructure view on considerations for persistent memory
and computational storage; and Andy
Walls of IBM, who presented a nice viewpoint of his vision of
computational storage and its underlying benefits that make the overall
infrastructure more rich and efficient, and how to bring compute to the drives. For a summary, watch Dave Eggleston of In-Cog
Computing who led Tuesday and Wednesday
panels with the mainstage speakers that provided a wide ranging discussion on
the Summit’s key topics.
SOS: What do you see as the top takeaways from
the Summit presenters?
DM: I see three:
Infrastructure,
applications, and use cases were paramount themes across a number of presentations
Tighter
coupling of technologies. Cheolmin Park
of Samsung, in his CXL
and UCIe presentation, discussed how we already have point
technologies that now need to interact together. There is also the Persistent Memory/SSD/DRAM
combination – a tiered memory configuration talked about for years. We are seeing deployment use cases where the
glue is interfacing the I/O technology with CXL and UCIe.
Another
takeaway strongly related to the above is heterogeneous operations and
compute. Compute can’t reside in one
central location for efficiency. Rather,
it must be distributed – addressing real-time analytics and decision making to
support applications.
SOS: What upcoming activities should Summit
viewers plan to attend and why?
DM: Put Flash Memory Summit, August 1-4, 2022 on your calendars. Here SNIA will go deeper into areas we explored at the Summit.
First, join SNIA Compute, Memory, and Storage Initiative (CMSI), underwriter of the PM+CS Summit, as we meet in person for the first time in a long time at the SNIA Reception on Monday evening August 1 at the Santa Clara Convention Center from 5:30 pm – 7:00 pm. Along with our SNIA teammates from the SNIA Storage Management Initiative, network with colleagues and share an appetizer or two as we gear up for three full days of activities.
At the Summit, the SNIA-sponsored System Architectures Track will feature a day on persistent memory, a day on CXL, and a day on computational storage. SNIA will also lead sessions on form factors, ethernet SSDs, sustainability, and DNA data storage. I am Track Manager of the Artificial Intelligence Applications Track, where we will see how technologies like computational storage and AI work hand-in-hand.
SNIA will have a Demonstration Pavilion at booth 725 in the FMS Exhibit Hall with live demonstrations of computational storage applications, persistent memory implementations, and scalable storage management with SNIA Alliance Partners; hands-on form factor displays; a Persistent Memory Programming Workshop and Hackathon; and theater presentations on standards. Full details are at www.flashmemorysummit.com
In September, CMSI will be at the SNIA Storage Developer
Conference where we will celebrate SNIA’s 25th anniversary and gather in person
for sessions, demonstrations, and those ever popular Birds-of-a-Feather
sessions. Find the latest details at www.storagedeveloper.org.
SOS: Any final thoughts?
DM: On behalf of SNIA CMSI and the PM+CS Summit Planning
Team, I’d like to thank all those who planned and attended our great
event. We are progressing in the right
direction, beginning to talk the same language that application developers and
solution providers understand. We’ll
keep building our strategic collaboration across different worlds at FMS and
SDC. I appreciate the challenges and
working together.
Our 10th annual Persistent Memory + Computational Storage Summit is right around the corner on May 24 and 25, 2022. We remain virtual this year, and hope this will offer you more flexibility to watch our live-streamed mainstage sessions, chat online, and catch our always popular Computational Storage birds-of-a-feather session on Tuesday afternoon without needing a plane or hotel reservation!
As David McIntyre of Samsung, the 2022 PM+CS Summit chair, says in his 2022 Summit Preview Video, “You won’t want to miss this event!”
This year, the Summit agenda expands knowledge on computational storage and persistent memory, and also features new sessions on computational memory, Compute Express Link TM (CXL)TM, NVM Express, SNIA Smart Data Accelerator Interface (SDXI), and Universal Chiplet Interconnect Express (UCIe).
We thank our many dynamic speakers who are presenting an exciting lineup of talks over the two days, including:
Yang Seok Ki of Samsung on Innovation with SmartSSD for Green Computing
Charles Fan of MemVerge on Persistent Memory Breaks Through the Clouds
Gary Grider of Los Alamos National Labs on HPC for Science Based Motivations for Computation Near Storage
Alan Benjamin of the CXL Consortium on Compute Express Link(CXL): Advancing the Next Generation of Data Centers
Cheolmin Park of Samsung on CXL and The Universal Chiplet Interconnect Express (UCIe)
Stephen Bates and Kim Malone of NVM Express on NVMe Computational Storage – An Update on the Standard
Andy Walls of IBM on Computational Storage for Storage Applications
We’ll have great networking opportunities, a virtual
reception, and the ability to connect with leading companies including Samsung,
MemVerge, and SMART Modular who are sponsoring the Summit.
The second webcast in our Storage Life on the Edge series is coming up on March 22, 2022 at 10:00 am Pacific time. This panel, moderated by Bill Martin, SNIA Compute, Memory, and Storage Initiative Chair, takes a deeper dive to focus on edge use cases in the computational storage space.
Our panelists Mayank Saxena from Samsung, Stephen Bates from Eideticom, and Tong Zhang from ScaleFlux will discuss edge to cloud use cases where storage and compute resources need to be deployed in practical topologies that deliver the very best in application performance. They’ll examine high performance edge data needs, database acceleration solutions, meeting retail chain challenges, and more. You won’t want to miss their panel discussion and the chance to ask your questions live.
Register here to attend. We’ll look forward to seeing you!
Our recent SNIA Compute, Memory, and Storage
Initiative (CMSI) webcast, Computational
Storage – Driving Success, Driving Standards,
explained the key elements of the SNIA Computational Storage Architecture and
Programming Model and the SNIA Computational Storage API . If you missed the
live event, you can watch
on-demand and view the presentation slides. Our
audience asked a number of questions, and Bill Martin, Editor of the Model, and
Jason Molgaard, Co-Chair of the SNIA Computational Storage Technical Work
Group, teamed up to answer them.
What’s being done in SNIA to implement data
protection (e.g. RAID) and CSDs? Can data be written/striped to CSDs in such a
way that it can be computed on within the drive?
Bill Martin: The
challenges of computation on a RAID system are outside the scope of the Computational
Storage Architecture and Programming Model. The Model does not
address data protection in that it does not specify how data is written nor how
computation is done on the data. Section
3 of the Model discusses the Computational Storage Array (CSA), a storage array
that is able to execute one or more Computational Storage Functions (CSFs). As
a storage array, a CSA contains control software, which provides virtualization
to storage services, storage devices, and Computational Storage Resources for
the purpose of aggregating, hiding complexity, or adding new capabilities to
lower level storage resources. The Computational Storage Resources in the CSA
may be centrally located or distributed across CSDs/CSPs within the array.
When will Version 1.0 of the Computational
Storage Architecture and Programming Model be available and when is operating
system support expected?
Bill Martin: We
expect Version 1.0 of the model to be available Q2 2022. The Model is agnostic with regard to
operating systems, but we anticipate a publicly available API library for
Computational Storage over NVMe.
Will Computational Storage library support CXL
accelerators as well? How is the collaboration between these two technology
consortiums?
Jason Molgaard: The Computational Storage Architecture and
Programming Model is agnostic to the device interface protocol. Computational Storage can work with CXL. SNIA
currently has an alliance
agreement in place with the CXL Consortium and will interface with that
group to help enable the CXL interface with Computational Storage. We anticipate there will be technical work to
develop a computational storage library utilizing the CS API that will support
CXL in the future.
System memory is required for PCIe/NVMe SSD.
How does computational storage bypass system memory?
Bill Martin: The computational storage architecture relies
on computation using memory that is local to the Computational Storage Device (CSx).Section
B.2.4 of the Model
describes the topic of Function Data Memory (FDM) on the CSx and the movement
of data from media to FDM and back. Note
that a device does not need to access system memory for computation – only to
read and write data. Figure B.2.8 from the Model illustrates CSx usage.
Is this CS API Library vendor
specific, or is this a generic library which could also be provided for example
by an operating system vendor?
Bill Martin: The Computational
Storage API is not a library, it is a generic interface
definition. It describes the software
application interface definitions for a Computational Storage device (CSx).There
will be a generic library for a given protocol layer, but there may also be
vendor specific additions to that generic library for vendor specific CSx
enhancements beyond the standard protocol definition.
Are there
additional use cases out there? Where could I see them and get more information?
Jason
Molgaard: Section B.2.5 of the Computational
Storage Architecture and Programming Model provides an example of application
deployment. The API specification will
have a library that could be used and/or modified for a specific device. If the
CSx does not support everything in NVMe, an individual could write a vendor
specific library that supports some host activity.
There are a lot of acronyms
and terms used in the discussion. Is
there a place where they are defined?
Jason Molgaard: Besides the Model and the API, which provide
the definitive definition of the terms and acronyms, there are some great
resources. Recent presentations at the
SNIA Storage Developer Conference on Computational Storage Moving Forward with an Architecture and
API
and Computational Storage APIs provide a broad view
of how the specifications affect the growing industry computational storage
efforts. Additional videos and presentations are available in the SNIA
Educational Library, search for “Computational
Storage”.
